公开(公告)号：US20220004455A1

公开(公告)日：2022-01-06

申请号：US17478597

申请日：2021-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-chu Oh ,  Moo-sung Kim ,  Young-sik Kim ,  Yong-jun Lee ,  Jeong-ho Lee

IPC: G06F11/10 ,  G06F11/07 ,  G11C29/52 ,  G11C13/00

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

公开(公告)号：US10818352B2

公开(公告)日：2020-10-27

申请号：US16413709

申请日：2019-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-gyu Lee ,  Yong-jun Lee ,  Bilal Ahmad Janjua ,  Chea-ouk Lim ,  Makoto Hirano

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.

公开(公告)号：US20200098427A1

公开(公告)日：2020-03-26

申请号：US16413709

申请日：2019-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-gyu Lee ,  Yong-jun Lee ,  Bilal Ahmad Janjua ,  Chea-ouk Lim ,  Makoto Hirano

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and a plurality bit lines to corresponding rows and columns of resistive memory cells in the array. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance associated therewith is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance associated therewith, which is greater than the first parasitic resistance.

公开(公告)号：US12105585B2

公开(公告)日：2024-10-01

申请号：US17478597

申请日：2021-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-chu Oh ,  Moo-sung Kim ,  Young-sik Kim ,  Yong-jun Lee ,  Jeong-ho Lee

IPC: G06F11/10 ,  G06F11/07 ,  G11C13/00 ,  G11C29/52

CPC classification number: G06F11/1044 ,  G06F11/076 ,  G06F11/1068 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0069 ,  G11C29/52

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

公开(公告)号：US11126497B2

公开(公告)日：2021-09-21

申请号：US16358884

申请日：2019-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-chu Oh ,  Moo-sung Kim ,  Young-sik Kim ,  Yong-jun Lee ,  Jeong-ho Lee

IPC: G06F11/10 ,  G11C29/52 ,  G06F11/07 ,  G11C13/00

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.