公开(公告)号：US20150270330A1

公开(公告)日：2015-09-24

申请号：US14732260

申请日：2015-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho LEE ,  Jin CHOI ,  Yong-Ho YOO ,  Jong-Hyuk KANG ,  Hyun-Joo CHA ,  Hee-Dong PARK ,  Tae-Jung PARK

IPC: H01L49/02

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/60

Abstract: A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.

Abstract translation: 半导体器件包括在基片上的多个下电极，其中每个下电极从衬底沿高度方向延伸并且包括侧壁，下电极在第一方向和第二方向彼此间隔开， 与下电极的侧壁接触的多个第一支撑层图案，第一支撑层图案沿着第一方向在第二方向上相邻的下电极之间延伸;多个第二支撑层图案，其与下部电极的侧壁接触; 电极，所述第二支撑层图案沿着所述第二方向在与所述第一方向相邻的所述下电极中的所述第二方向延伸，所述多个第二支撑层图案在所述高度方向上与所述多个第一支撑层图案间隔开。

公开(公告)号：US20160181251A1

公开(公告)日：2016-06-23

申请号：US14973649

申请日：2015-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Ho YOO ,  Tae-jung PARK

IPC: H01L27/108 ,  H01L27/02 ,  H01L29/06 ,  G11C11/4091 ,  H01L23/528

CPC classification number: H01L29/0649 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/565 ,  H01L27/108 ,  H01L27/10844 ,  H01L28/90

Abstract: A semiconductor device includes a first memory cell including a first transistor and a first capacitor, the first transistor comprising a first gate electrode, a first source, and a first drain; a second memory cell including a second transistor and the first capacitor, the second transistor comprising a second gate electrode, a second source, and a second drain; a first word line coupled to the first gate electrode; and a second word line coupled to the second gate electrode. The first capacitor is electrically connected between the first and second transistors.

Abstract translation: 半导体器件包括：第一存储单元，包括第一晶体管和第一电容器，第一晶体管包括第一栅电极，第一源极和第一漏极; 第二存储单元，包括第二晶体管和第一电容器，第二晶体管包括第二栅电极，第二源极和第二漏极; 耦合到所述第一栅电极的第一字线; 以及耦合到所述第二栅电极的第二字线。 第一电容器电连接在第一和第二晶体管之间。