公开(公告)号：US20230387088A1

公开(公告)日：2023-11-30

申请号：US18069318

申请日：2022-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： YeongBeom Ko ,  Junyun Kweon

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L25/105 ,  H01L23/5383 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/16 ,  H01L23/3107 ,  H01L23/49811 ,  H01L25/0657 ,  H01L24/14 ,  H01L24/73 ,  H01L24/05 ,  H01L24/94 ,  H01L21/561 ,  H01L2224/0401 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/94

Abstract: A semiconductor package includes at least one semiconductor module on a substrate. The semiconductor module includes a first semiconductor chip having a first surface and a second surface opposite to the first surface, a second semiconductor chip on the first surface, a plurality of conductive pillars on the first surface, and a redistribution substrate on the second semiconductor chip and the plurality of conductive pillars. The redistribution substrate has a third surface and a fourth surface opposite to the third surface. The third surface of the redistribution substrate faces the first surface of the first semiconductor chip, the plurality of conductive pillars are electrically connected to the first surface of the first semiconductor chip and the third surface of the redistribution substrate, and the fourth surface of the redistribution substrate is electrically connected to the substrate of the semiconductor package.

公开(公告)号：US12300667B2

公开(公告)日：2025-05-13

申请号：US17692693

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YeongBeom Ko

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: Provided is a semiconductor package, including a lower semiconductor chip, a plurality of semiconductor chips that are disposed on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip, a plurality of nonconductive layers disposed between the plurality of semiconductor chips, a nonconductive pattern that extends from the nonconductive layers and is disposed on lateral surfaces of at least one of the plurality of semiconductor chips, a first mold layer disposed a top surface of the nonconductive pattern, and a second mold layer disposed a lateral surface of the nonconductive pattern and a lateral surface of the first mold layer, wherein the nonconductive pattern and the first mold layer are disposed between the second mold layer and lateral surfaces of the plurality of semiconductor chips.