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公开(公告)号：US20220107661A1
公开(公告)日：2022-04-07
申请号：US17200017
申请日：2021-03-12
Inventor： Chisung BAE , Hyungmin GI , Yeohoon YOON , Yoonmyung LEE
Abstract: An apparatus and method for tracking maximum power are disclosed. The apparatus is configured to track a maximum power at a certain node of an electronic circuit, adjust an impedance of the electronic circuit such that power at the node is maximal, and adjust an impedance of the electronic circuit by comparing power at two points in time to increase power. The apparatus for tracking a maximum power, includes a charge sharing capacitor connected to an initial capacitor in parallel, a first switch disposed between the initial capacitor and an energy harvesting power supply, a second switch disposed between the initial capacitor and the charge sharing capacitor, a third switch disposed between the energy harvesting power supply and a comparator, and a switched-capacitor power converting circuit configured to control the initial capacitor.
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公开(公告)号：US20230072616A1
公开(公告)日：2023-03-09
申请号：US17697243
申请日：2022-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeohoon YOON , Ilho KIM
IPC: H01L23/538 , H01L23/31 , H01L23/00
Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip spaced apart from the first semiconductor chip, an adhesive layer including an interposition portion and a side portion, and a molding layer. The molding layer may surround the first semiconductor chip, the second semiconductor chip, and the adhesive layer. The interposition portion may be between the first and second semiconductor chips. The side portion may contact a side surface of the first semiconductor chip and a side surface of the second semiconductor chip. A top surface of the side portion is curved, and an outer side surface of the side portion is flat.
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公开(公告)号：US20250125271A1
公开(公告)日：2025-04-17
申请号：US19001810
申请日：2024-12-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeohoon YOON , Ilho KIM
IPC: H01L23/538 , H01L23/00 , H01L23/31
Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip spaced apart from the first semiconductor chip, an adhesive layer including an interposition portion and a side portion, and a molding layer. The molding layer may surround the first semiconductor chip, the second semiconductor chip, and the adhesive layer. The interposition portion may be between the first and second semiconductor chips. The side portion may contact a side surface of the first semiconductor chip and a side surface of the second semiconductor chip. A top surface of the side portion is curved, and an outer side surface of the side portion is flat.
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公开(公告)号：US20230021362A1
公开(公告)日：2023-01-26
申请号：US17714714
申请日：2022-04-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yeohoon YOON , Ilho Kim
IPC: H01L23/00
Abstract: A semiconductor package is provided. The semiconductor package includes a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure including an insulating layer and a redistribution conductor provided in the insulating layer; a semiconductor chip provided on the rear surface and including a connection pad electrically connected to the redistribution conductor; an encapsulant provided on at least a portion of the semiconductor chip; under-bump metal (UBM) vias extending from the redistribution conductor to the front surface of the redistribution structure within the insulating layer; UBM pads provided on the front surface of the redistribution structure to correspond to the UBM vias, respectively, and each UMB pad of the UBM pads having an exposed surface convexly protruding away from the front surface of the redistribution structure; and a metal bump provided on the UBM pads and contacting the exposed surface of each UMB pad of the UBM pads.
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