公开(公告)号：US12079491B2

公开(公告)日：2024-09-03

申请号：US18150626

申请日：2023-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewoo Han ,  Wooil Kim ,  Taehun Kim

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.

公开(公告)号：US20230266893A1

公开(公告)日：2023-08-24

申请号：US18150626

申请日：2023-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewoo Han ,  Wooil Kim ,  Taehun Kim

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.