公开(公告)号：US10922171B2

公开(公告)日：2021-02-16

申请号：US16441287

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hye Cho ,  Ki-Jun Lee ,  Myung-Kyu Lee ,  Jun Jin Kong

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/00 ,  G11C29/52

Abstract: An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.