公开(公告)号：US20210233879A1

公开(公告)日：2021-07-29

申请号：US17229023

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il CHOI ,  Kwangjin MOON ,  Sujeong PARK ,  JuBin SEO ,  Jin Ho AN ,  Dong-chan LIM ,  Atsushi FUJISAKI

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US20250046740A1

公开(公告)日：2025-02-06

申请号：US18637827

申请日：2024-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jubin SEO ,  Dongchan LIM ,  Sujeong PARK ,  Junkyoung LEE

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor chip structure includes a plurality of semiconductor chips. A bonding electrode included in each of the semiconductor chips is filled with nanotwin copper and fine grain copper is disposed in at least a portion of the bonding electrode.