公开(公告)号：US20170041086A1

公开(公告)日：2017-02-09

申请号：US15223524

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Beom PARK ,  Hong Sik PARK ,  Jong Hyup LEE

IPC: H04B15/02 ,  H04B17/00 ,  H03L7/07

CPC classification number: H04B15/02 ,  H03L7/22 ,  H04B17/0085

Abstract: In an example embodiment, a data transmission apparatus includes a transmission link module configured to generate a reference clock signal and a transmission D-PHY module. The transmission D-PHY module includes a first phase locked loop configured to receive the reference clock signal, and generate a first clock signal. The transmission D-PHY module further includes a second phase locked loop configured to receive the reference clock signal, and generate a second clock signal having a different frequency than the first clock signal. The transmission D-PHY module further includes a multiplexer configured to select and output one of the first and second clock signals as a clock signal according to a selection signal. The transmission D-PHY module further includes a data transmitter configured to convert parallel data into serial data in response to the clock signal for transmission to a receiver.

Abstract translation: 在示例实施例中，数据传输装置包括被配置为产生参考时钟信号和传输D-PHY模块的传输链路模块。 传输D-PHY模块包括被配置为接收参考时钟信号并产生第一时钟信号的第一锁相环。 传输D-PHY模块还包括被配置为接收参考时钟信号并产生具有与第一时钟信号不同的频率的第二时钟信号的第二锁相环。 传输D-PHY模块还包括多路复用器，其被配置为根据选择信号选择并输出第一和第二时钟信号中的一个作为时钟信号。 传输D-PHY模块还包括数据发射机，其被配置为响应于时钟信号将并行数据转换为串行数据，以传输到接收机。