公开(公告)号：US20230075320A1

公开(公告)日：2023-03-09

申请号：US17732947

申请日：2022-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Noyoung CHUNG ,  Taekyum KIM ,  Hyunyong JEONG ,  Sang-Hwa LEE ,  Byung Je JUNG

IPC: H01L29/786 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a logic cell on a substrate, and a first metal layer on the logic cell. The first metal layer includes first and second power lines and first to third lower lines on first to third wiring tracks therebetween. The first to third wiring tracks extend in parallel in the first direction. The first lower line includes first and second lines spaced apart in the first direction from each other at a first distance. The third lower line includes third and fourth lines spaced apart in the first direction at a second distance. The first line has a first end facing the second line. The third line has a second end facing the fourth line. A curvature at the first end is substantially the same as that at the second end.

公开(公告)号：US20240193755A1

公开(公告)日：2024-06-13

申请号：US18526242

申请日：2023-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungkee CHOI ,  Noyoung CHUNG

IPC: G06T7/00 ,  G06T7/11

CPC classification number: G06T7/0006 ,  G06T7/11 ,  G01N2223/401 ,  G01N2223/611 ,  G06T2207/10061 ,  G06T2207/20021 ,  G06T2207/30148

Abstract: A pattern defect inspection device includes an inspection apparatus inspecting a pattern on a substrate, a database storing a pattern layout including a plurality of defect patterns from the inspection apparatus, a preset field of view (FOV) size, and a target measurement number, and a processor setting a plurality of inspection regions of the inspection apparatus based on the pattern layout, wherein the processor includes a defect search unit searching for a region defect pattern existing in any one of a plurality of inspection regions in the pattern layout, an inspection region aligning unit arranging the plurality of inspection regions based on the region defect pattern, an overlapping region removal unit removing an overlapping region from the plurality of inspection regions, and an inspection region selecting unit selecting an inspection region other than the overlapping region, among the plurality of inspection regions, as a final inspection region.

公开(公告)号：US20170139317A1

公开(公告)日：2017-05-18

申请号：US15334508

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin SHIN ,  Noyoung CHUNG

IPC: G03F1/36

CPC classification number: G03F1/36

Abstract: A mask fabricating method includes dividing an outline of a first design layout for a target layer into plural segments, selecting interest segments to be biased in a direction of approaching an outline of a second design layout for a lower layer of the target layer, performing optical proximity correction for the target layer based on a first cost function given to each of normal segments and a second cost function given to each of the interest segments, and fabricating the mask corresponding to the first design layout updated based on a result of the optical proximity correction. The second cost function includes a model of a margin between each of the interest segments and the outline of the second design layout. Performing the optical proximity correction includes biasing each of the interest segments up to a boundary defined by the margin.

公开(公告)号：US20230055365A1

公开(公告)日：2023-02-23

申请号：US17692438

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseok KIM ,  Noyoung CHUNG ,  Byung Je JUNG

IPC: G03F1/36 ,  G06F30/398

Abstract: A method includes grouping, in a first layout, pattern regions which have duplicate layout patterns including weak regions as a group, calculating defect probabilities of the pattern regions, respectively, calculating a defect frequency and a defect rate of the group based on the defect probabilities of the pattern regions, predicting a degree of defects of a second layout of the pattern regions, based on the defect frequency and the defect rate, and performing an extreme ultraviolet (EUV) lithography process on a substrate, based on the second layout. The defect probabilities are calculated by performing an optical proximity correction (OPC) simulation on the pattern region, calculating a stochastic variation of a linewidth of a simulation pattern in the weak region as a Gaussian distribution, and defining a threshold linewidth, which is used as a reference of the random defect, in the Gaussian distribution.

公开(公告)号：US20220292245A1

公开(公告)日：2022-09-15

申请号：US17554517

申请日：2021-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Akio MISAKA ,  Jongdoo KIM ,  Noyoung CHUNG

IPC: G06F30/392 ,  G06F30/398 ,  H01L27/02 ,  G03F7/20

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes generating a first virtual layout by placing and routing standard cells using a virtual netlist, searching first duplicate pattern regions in the first virtual layout and choosing one of them as a first representative pattern region, performing an OPC operation on the first representative pattern region to obtain a first OPC result, generating an actual layout by placing and routing standard cells using an actual netlist, performing an OPC operation on the actual layout, and forming a photoresist pattern on a substrate using a photomask manufactured based on the actual layout, to which the OPC operation is applied.

公开(公告)号：US20220121107A1

公开(公告)日：2022-04-21

申请号：US17360365

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Akio MISAKA ,  Changsoo KIM ,  Noyoung CHUNG

IPC: G03F1/36 ,  G06F30/392

Abstract: A non-transitory computer-readable medium storing codes that, when executed by a processor, cause the processor to perform operations of receiving full chip data including specific patterns of a first layout, extracting a representative pattern of the first layout from the full chip data, generating a vector of the extracted representative pattern, generating a first data set based on the generated vector, generating a machine learning model by performing machine learning with respect to the first data set, executing an optical proximity correction (OPC) with respect to the specific patterns of the first layout by using the machine learning model, and generating a second layout based on a result of executing the OPC may be provided.

公开(公告)号：US20220057707A1

公开(公告)日：2022-02-24

申请号：US17236440

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeong Seop KIM ,  Noyoung CHUNG

IPC: G03F1/36 ,  H01L21/027 ,  H01L21/285 ,  H01L21/8238 ,  G06F30/392

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes performing an optical proximity correction (OPC) on design patterns of a layout to generate a corrected layout, and forming a photoresist pattern on a substrate using a photomask manufactured based on the corrected layout. The OPC comprises generating develop targets for the design patterns, respectively, choosing first object patterns based on distances between the develop targets, performing a first OPC operation on the design patterns based on a mask rule to generate first correction patterns, choosing second object patterns by considering distances between the first correction patterns and a target error of each of the first correction patterns, and performing a second OPC operation on the first and second object patterns to generate second correction patterns, the performing the second OPC not based on the mask rule.