公开(公告)号：US20250167175A1

公开(公告)日：2025-05-22

申请号：US19027183

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minkyeong PARK ,  Do-Hyun KIM ,  Jaekyu SUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

公开(公告)号：US20230005884A1

公开(公告)日：2023-01-05

申请号：US17665810

申请日：2022-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyeong PARK ,  Do-Hyun KIM ,  Jaekyu SUNG

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.