公开(公告)号：US12167158B2

公开(公告)日：2024-12-10

申请号：US18062853

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehwa Paik ,  Cyuyeol Rhee ,  Kyungil Kim ,  Jaehong Kim ,  Jinwoo Kim ,  Seunghyun Lim ,  Sanghyun Cho

IPC: H04N25/78 ,  H04N25/709

Abstract: An analog-to-digital converting circuit includes a first amplifier configured to output a first output signal by comparing a pixel signal output from a pixel array with a ramp signal, and a second amplifier configured to generate a second output signal based on the first output signal. The second amplifier includes a first transistor configured to provide a power supply voltage to a first output node in response to the first output signal, a second transistor connected with a capacitor through a bias node, wherein the second transistor is configured to turn on in response to an auto-zero signal, a current source connected with the first transistor through the first output node, the current source configured to generate a power current based on a voltage level of the bias node, and a third transistor connected with the current source.

公开(公告)号：US20240212214A1

公开(公告)日：2024-06-27

申请号：US18392713

申请日：2023-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseok LEE ,  Kyungil Kim

IPC: G06T9/00

CPC classification number: G06T9/00

Abstract: An image processing device includes an interface configured to receive compressed data obtained by compressing image data corresponding to an output of at least one pixel and a decoder configured to generate at least two different pieces of compensation data based on loss data included in the compressed data and generate decompressed data by decompressing the compressed data based on any one piece of compensation data among the at least two different pieces of compensation data, where the loss data corresponds to data lost due to compression of the image data.

公开(公告)号：US20230345152A1

公开(公告)日：2023-10-26

申请号：US18062853

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehwa Paik ,  Cyuyeol Rhee ,  Kyungil Kim ,  Jaehong Kim ,  Jinwoo Kim ,  Seunghyun Lim ,  Sanghyun Cho

IPC: H04N25/78 ,  H04N25/709

CPC classification number: H04N25/78 ,  H04N25/709

Abstract: An analog-to-digital converting circuit includes a first amplifier configured to output a first output signal by comparing a pixel signal output from a pixel array with a ramp signal, and a second amplifier configured to generate a second output signal based on the first output signal. The second amplifier includes a first transistor configured to provide a power supply voltage to a first output node in response to the first output signal, a second transistor connected with a capacitor through a bias node, wherein the second transistor is configured to turn on in response to an auto-zero signal, a current source connected with the first transistor through the first output node, the current source configured to generate a power current based on a voltage level of the bias node, and a third transistor connected with the current source.