INTEGRATED CIRCUIT FOR COMPUTING TARGET ENTRY ADDRESS OF BUFFER DESCRIPTOR BASED ON DATA BLOCK OFFSET, METHOD OF OPERATING SAME, AND SYSTEM INCLUDING SAME
    2.
    发明申请
    INTEGRATED CIRCUIT FOR COMPUTING TARGET ENTRY ADDRESS OF BUFFER DESCRIPTOR BASED ON DATA BLOCK OFFSET, METHOD OF OPERATING SAME, AND SYSTEM INCLUDING SAME 有权
    用于基于数据块偏移来计算缓冲器描述符的目标地址的集成电路,其操作方法和包括其的系统

    公开(公告)号:US20140244908A1

    公开(公告)日:2014-08-28

    申请号:US14144682

    申请日:2013-12-31

    CPC classification number: G06F12/06 G06F12/0292

    Abstract: A method of operating an integrated circuit is provided. The method includes receiving a data block offset from a second storage device, obtaining a target entry address using the data block offset, and reading an entry among a plurality of entries comprised in a buffer descriptor stored in a first storage device based on the target entry address. The method also includes reading data from a data buffer among a plurality of data buffers included in the first storage device using a physical address included in the entry and transmitting the data to the second storage device.

    Abstract translation: 提供一种操作集成电路的方法。 该方法包括从第二存储设备接收数据块偏移量,使用数据块偏移获取目标条目地址,以及基于目标条目读取包含在存储在第一存储设备中的缓冲器描述符中的多个条目中的条目 地址。 该方法还包括使用包含在条目中的物理地址从包括在第一存储装置中的多个数据缓冲器中的数据缓冲器读取数据,并将数据发送到第二存储装置。

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