公开(公告)号：US20230042955A1

公开(公告)日：2023-02-09

申请号：US17689064

申请日：2022-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Min YOU ,  Ho-Youn KIM ,  Won-Hyung SONG ,  Hi Jung KIM

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device includes memory cells connected to a first word-line, wherein the memory cells include a data region in which data is stored and a counting value backup region in which the number of times the first word-line is activated is backed up, a counting table for storing a first row address corresponding to the first word-line and a first counting value as a counting result of the number of times the first word-line is activated, and a comparator configured to compare the first counting value with a first backed-up counting value stored in the counting value backup region; and when the first counting value is greater than the first backed-up counting value, back up the first counting value in the counting value backup region, or when the first backed-up counting value is greater than the first counting value, overwrite the first backed-up counting value into the counting table.

公开(公告)号：US20250156544A1

公开(公告)日：2025-05-15

申请号：US18662995

申请日：2024-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNGKYU LEE ,  Eun Ae Lee ,  SUNGHYE CHO ,  Jung Min YOU ,  KYOMIN SOHN ,  KIJUN LEE

IPC: G06F21/56

Abstract: A memory device may include an attack row selector configured to receive an activation signal at a first time point, and generate an update signal based on an accumulation value, an attack row register configured to receive an activation row address corresponding to the activation signal, and determine an attack row address based on the update signal and the activation row address, and a victim row determiner configured to determine a victim row address based on the attack row address. The accumulation value may be the number of activation signals received from a second time point before the first time point to the first time point.

公开(公告)号：US20230146377A1

公开(公告)日：2023-05-11

申请号：US17885822

申请日：2022-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Min YOU ,  Seong-Jin CHO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673 ,  G06F12/0238 ,  G06F2212/70

Abstract: According to an embodiment, a memory device includes a memory cell array including a plurality of memory cells; and a control logic which includes a mode register, performs a refresh operation in response to a refresh command, generates an internal mode register write command in response to the refresh command in a first mode, and does not generate the internal mode register write command in response to the refresh command in a second mode.

公开(公告)号：US20230223073A1

公开(公告)日：2023-07-13

申请号：US17953524

申请日：2022-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hijung KIM ,  Jung Min YOU ,  Seong-Jin CHO

IPC: G11C11/4096 ,  G11C11/408 ,  G11C17/16

CPC classification number: G11C11/4096 ,  G11C11/408 ,  G11C17/165

Abstract: Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.