公开(公告)号：US09184091B2

公开(公告)日：2015-11-10

申请号：US14101631

申请日：2013-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo-Young Song ,  Cheol-Ju Yun ,  Seung-Hee Ko ,  Jina Kim ,  Hyun-Gi Kim ,  Chae-Ho Lim

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L21/7682 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.

Abstract translation: 第一掺杂区域和第二掺杂剂区域设置在栅极结构的两侧。 导电线在栅极结构上交叉并连接到第一掺杂区。 每个导线包括导电图案和设置在导电图案上的封盖图案。 在导线之间提供接触结构，并连接到第二掺杂剂区域。 每个接触结构包括设置在第二掺杂剂区域上的下接触图案和设置在下接触图案上的上接触图案。 上触点图案的底表面低于导电图案的顶表面。

公开(公告)号：US20240040770A1

公开(公告)日：2024-02-01

申请号：US18194642

申请日：2023-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jina Kim ,  Kang-Uk Kim ,  Ho-In Ryu ,  Yunho Song ,  Dalhyeon Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/485

Abstract: A memory device includes a substrate having first and second active patterns adjacent to each other and separated by a trench, the first and second active patterns including a first source/drain region; the second active pattern includes a second source/drain region. The second source/drain region includes first and second sidewall surfaces adjacent the first source/drain region and a connecting surface that connects the first and second sidewall surfaces. The second sidewall surface is set back from the first sidewall surface. An isolation layer is included in the trench and on the first sidewall surface. A bit line includes a contact part connected to the first source/drain region. A contact is coupled to the second source/drain region with a lower spacer between the contact and the contact part of the bit line, a landing pad on the contact, and a data storage element on the landing pad.