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公开(公告)号:US20230038036A1
公开(公告)日:2023-02-09
申请号:US17881228
申请日:2022-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yuri CHOI , Changhwan KIM , Sungchan BAE , Jieun JEONG
IPC: G06F9/451 , G06F3/04883 , G06F3/0486 , G06F3/04845
Abstract: An electronic device is disclosed and includes a display and at least one processor operatively connected with the display. The at least one processor is configured to, when an application is executed, display an execution window corresponding to the application on the display, display the execution window, as a first shape of execution window, on at least a portion of the display, in response to a background switch request for the application, identify a state of the application while displaying the first shape of execution window, and switch the first shape of execution window into a second shape of execution window according to the state of the application.
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公开(公告)号:US20210311896A1
公开(公告)日:2021-10-07
申请号:US17347769
申请日:2021-06-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jiwoong KIM , Dongjoo KIM , Jaekuk PARK , Yujin OH , Moonki JANG , Jieun JEONG
Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.
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