公开(公告)号：US11355498B2

公开(公告)日：2022-06-07

申请号：US16902506

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaybok Choi ,  Yongseok Ahn ,  Seunghyung Lee

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762 ,  H01L21/306

Abstract: A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.

公开(公告)号：US11963344B2

公开(公告)日：2024-04-16

申请号：US17744026

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaybok Choi ,  Yongseok Ahn ,  Seunghyung Lee

IPC: H10B12/00 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762

CPC classification number: H10B12/053 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76224 ,  H10B12/34

Abstract: A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.

公开(公告)号：US20230005926A1

公开(公告)日：2023-01-05

申请号：US17839344

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkwan Yang ,  Jaybok Choi ,  Yongseok Ahn

IPC: H01L27/108

Abstract: An integrated circuit device includes: a plurality of bit lines extending on a substrate in a first direction parallel to an upper surface of the substrate; a plurality of insulation capping structures respectively arranged on the plurality of bit lines, extending in the first direction, and including a first insulating material; a conductive plug between two adjacent bit lines among the plurality of bit lines on the substrate; a top capping layer arranged on the plurality of insulation capping structures and including a second insulating material different from the first insulating material; and a landing pad arranged on the conductive plug and arranged on a sidewall of a corresponding insulation capping structure among the plurality of insulation capping structures and the top capping layer.