公开(公告)号：US20240362178A1

公开(公告)日：2024-10-31

申请号：US18485706

申请日：2023-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseok YANG ,  Yunkyeong JEONG ,  Jaewoo SHIN ,  Minhwan AN ,  Jin Suk CHUNG

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/4022

Abstract: A memory device includes a first physical interface, a second physical interface, a first memory core, a second memory core, and a setting circuit. The first memory core is assigned to the first physical interface and includes a plurality of first stacked memory dies and connected via a through electrode. The second memory core is assigned to the second physical interface and includes a plurality of second stacked memory dies connected via a through electrode. The setting circuit sets at least one physical interface to be used for connection with an external device of the memory device among the first physical interface and the second physical interface.