公开(公告)号：US10962581B2

公开(公告)日：2021-03-30

申请号：US16575805

申请日：2019-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Nyeong Yun ,  Jae Moo Choi ,  Jong Pill Park ,  Jae Hong Kim

IPC: G01R31/01 ,  G01R31/28 ,  G01R1/073 ,  G01R31/319

Abstract: A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

公开(公告)号：US10444270B2

公开(公告)日：2019-10-15

申请号：US15455818

申请日：2017-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Nyeong Yun ,  Jae Moo Choi ,  Jong Pill Park ,  Jae Hong Kim

IPC: G01R31/01 ,  G01R31/28 ,  G01R1/073 ,  G01R31/319

Abstract: A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

公开(公告)号：US09293226B2

公开(公告)日：2016-03-22

申请号：US14341856

申请日：2014-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hyun Baek ,  Jae Moo Choi ,  Jae Hee Han ,  In Su Yang ,  Hyun Soo Jung

IPC: G11C29/00 ,  G11C29/56

CPC classification number: G11C29/56004

Abstract: A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.

Abstract translation: 提供了一种用于测试存储器件的存储器测试装置。 存储器测试装置包括定序器，其被配置为响应于定序器输入而输出彼此不同的第一和第二定序器输出。 第一模式发生器被配置为根据第一定序器输出输出第一测试模式。 第二模式发生器被配置为根据第二定序器输出输出第二测试模式。 选择器耦合到第一和第二图案发生器并且被配置为根据第一测试图案和第二测试图案来输出写入数据。