公开(公告)号：US20250048642A1

公开(公告)日：2025-02-06

申请号：US18587355

申请日：2024-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il Ho MYEONG ,  Su Seong NOH ,  Seung Min LEE ,  Sang Woo HAN

IPC: H10B51/20 ,  H10B51/30

Abstract: A semiconductor memory device includes a substrate, a mold structure including a plurality of gate electrodes and a plurality of mold insulating films alternately stacked on the substrate, a channel structure extending in a first direction and penetrating the mold structure, the channel structure including a semiconductor pattern and a ferroelectric film between the semiconductor pattern and the plurality of gate electrodes, a channel pad on the channel structure, and a bit line contact connected to the channel pad, wherein an uppermost part of the ferroelectric film protrudes beyond an uppermost gate electrode among the plurality of gate electrodes, the channel pad includes a first portion in contact with the semiconductor pattern and a second portion in contact with the first portion and the bit line contact, the first portion has a first width, and the second portion has a second width greater than the first width.