公开(公告)号：US20230176678A1

公开(公告)日：2023-06-08

申请号：US18091137

申请日：2022-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunkeun SONG ,  Seungjun LEE

IPC: G06F3/041 ,  G06F3/01 ,  G06F3/04883

CPC classification number: G06F3/0416 ,  G06F3/017 ,  G06F3/04883

Abstract: An electronic device according to the disclosure may include: a display including a first area and a second area; a first sensor and a second sensor disposed oppositely on at least a part of or an adjacent side surface corresponding to the first area and the second area of the display, each of the first sensor and the second sensor configured to detect a grip; and a processor operatively connected to the display, the first sensor, and the second sensor, wherein the processor is configured to: detect a grip based on a sensor value change of one of the first sensor or the second sensor, receive a touch input sensed in at least a partial area of one of the first area or the second area of the display corresponding to the sensor among the first sensor or the second sensor detecting the grip, and convert into a touch input targeting an entire area of the display including the first area and the second area.

公开(公告)号：US20210173756A1

公开(公告)日：2021-06-10

申请号：US17118071

申请日：2020-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suha YOON ,  Mooyoung KIM ,  Minjung KIM ,  Hyunkeun SONG

IPC: G06F11/30 ,  G06F11/07 ,  G06F13/42 ,  G06F1/3215

Abstract: An apparatus and method for controlling an interface between a plurality of processors in an electronic device are disclosed. The electronic device may include: a first integrated circuit; a second integrated circuit; and a Peripheral Component Interconnect Express (PCIe) interface interconnecting the first integrated circuit and the second integrated circuit, wherein the first integrated circuit may be configured to identify the required latency level associated with a service provided by the electronic device, and restrict the use of at least one power mode among a plurality of power modes supported by the PCIe interface, based on the required latency level associated with the service. Additional embodiments are possible.