公开(公告)号：US20210272623A1

公开(公告)日：2021-09-02

申请号：US17322227

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20140231892A1

公开(公告)日：2014-08-21

申请号：US14101631

申请日：2013-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo-Young SONG ,  Cheol-Ju YUN ,  Seung-Hee KO ,  Jina KIM ,  Hyun-Gi KIM ,  Chae-Ho LIM

IPC: H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.

Abstract translation: 第一掺杂区域和第二掺杂剂区域设置在栅极结构的两侧。 导电线在栅极结构上交叉并连接到第一掺杂区。 每个导线包括导电图案和设置在导电图案上的封盖图案。 在导线之间提供接触结构，并连接到第二掺杂剂区域。 每个接触结构包括设置在第二掺杂剂区域上的下接触图案和设置在下接触图案上的上接触图案。 上触点图案的底表面低于导电图案的顶表面。

公开(公告)号：US20200168269A1

公开(公告)日：2020-05-28

申请号：US16779194

申请日：2020-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20210005247A1

公开(公告)日：2021-01-07

申请号：US17024259

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20190371391A1

公开(公告)日：2019-12-05

申请号：US16228518

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.