公开(公告)号：US12013797B2

公开(公告)日：2024-06-18

申请号：US18050098

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ikkyun Park ,  Soongmann Shin ,  Gyuseok Choe

IPC: G06F13/16 ,  G06F9/48 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F13/1668 ,  G06F9/4881 ,  G06F11/076 ,  G06F11/3037 ,  G06F11/3058 ,  G06F13/1605

Abstract: An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips; obtaining information about an operation status of each of the plurality of memory chips; and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips.

公开(公告)号：US11531630B2

公开(公告)日：2022-12-20

申请号：US17078194

申请日：2020-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ikkyun Park ,  Soongmann Shin ,  Gyuseok Choe

IPC: G06F13/16 ,  G06F11/30 ,  G06F11/07 ,  G06F9/48

Abstract: An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips; obtaining information about an operation status of each of the plurality of memory chips; and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips.

公开(公告)号：US20220197510A1

公开(公告)日：2022-06-23

申请号：US17395582

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngmin Lee ,  Changjun Lee ,  Jinmyung Yoon ,  Gyuseok Choe ,  Seongwan Hong

IPC: G06F3/06

Abstract: An operating method of a storage device, including a core and a memory, includes receiving a first processing code configured to enable execution of a first task and storing the first processing code in a first logical unit separately allocated in the memory for near-data processing (NDP), in response to a write command received from a host device, activating the core for executing the first processing code, in response to an activation command received from the host device, and executing the first task by using the core, in response to an execution command received from the host device.