公开(公告)号：US20240188281A1

公开(公告)日：2024-06-06

申请号：US18529449

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gangjun KIM

IPC: H10B12/00 ,  H01L29/423

CPC classification number: H10B12/34 ,  H01L29/4236 ,  H01L29/4238 ,  H10B12/0335 ,  H10B12/50

Abstract: An integrated circuit device includes a substrate including an element isolation film defining an active area, and a gate structure buried in the active area of the substrate. The gate structure includes a gate trench, an outer insulating layer conformed along an inner wall of the gate trench, a channel structure layer conformed on the outer insulating layer, a gate insulating layer conformed on the channel structure layer, a gate electrode layer filling a lower area of the gate trench, and a capping insulating layer on the gate electrode layer, the capping insulating layer filling an upper area of the gate trench.

公开(公告)号：US20250149397A1

公开(公告)日：2025-05-08

申请号：US18732276

申请日：2024-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonhaeng LEE ,  Gangjun KIM

IPC: H01L23/34 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

Abstract: A semiconductor device includes a substrate having a device region including a memory cell region and a peripheral circuit region, and a heating region surrounding the device region, a heating structure disposed in the heating region of the substrate, the heating structure surrounding the device region in a plan view, and a temperature control device electrically connected to the heating structure. The peripheral circuit region includes a peripheral gate structure. The heating structure includes a first lower structure disposed at about a same level as the peripheral gate structure. The first lower structure includes a lower dielectric layer, and a conductive layer including polysilicon disposed on the lower dielectric layer.