公开(公告)号：US12237252B2

公开(公告)日：2025-02-25

申请号：US17672092

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Jeon ,  Joonseok Oh ,  Youngmin Kim ,  Dongheon Kang ,  Changbo Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package may include at least one first rewiring structure, the at least one first rewiring structure including a plurality of first insulating layers vertically stacked and a plurality of first rewiring patterns included in the plurality of first insulating layers, at least one semiconductor chip on the at least one first rewiring structure, and at least one molding layer covering the at least one semiconductor chip, wherein each of the plurality of first rewiring patterns includes, a first conductive pattern, the first conductive pattern including a curved upper surface, and a first seed pattern covering a side surface and a lower surface of the first conductive pattern, and each of the first seed patterns of the plurality of first rewiring patterns having a same shape.