公开(公告)号：US20160013927A1

公开(公告)日：2016-01-14

申请号：US14489986

申请日：2014-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： June-Hee LEE ,  Jongshin SHIN ,  Youngkyun JEONG ,  Dongchul CHOI

IPC: H04L7/033 ,  H04L27/22

CPC classification number: H04L7/033 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H04L27/22

Abstract: A clock data recovery circuit includes a sampler to sample incoming data bits, a phase detector to generate an edge position signal and a polarity signal based on the sampled incoming data, a finite state machine to save a current edge position state, a polarity decision unit to generate a polarity inversion signal to invert the polarity signal, a gain controller to generate a tracking bandwidth signal, a recovery loop configured to adjust an edge offset of the reference clock, and a bit selector configured to recover the incoming data. The clock data recovery circuit has a first latency at a first operation mode and a second latency at a second operation mode. The phase detector in the clock data recovery circuit may include a first phase detector and a second detector combined together for a low latency and low lock time of the clock data recovery circuit.

Abstract translation: 时钟数据恢复电路包括：采样器，用于对输入的数据位进行采样;相位检测器，用于根据采样的输入数据产生边沿位置信号和极性信号;有限状态机，用于保存当前边沿位置状态;极性判定单元 产生极性反转信号以反转极性信号，增益控制器产生跟踪带宽信号;恢复环路，被配置为调整参考时钟的边沿偏移;以及位选择器，被配置为恢复输入数据。 时钟数据恢复电路在第一操作模式下具有第一等待时间，在第二操作模式下具有第二等待时间。 时钟数据恢复电路中的相位检测器可以包括第一相位检测器和第二检测器，其组合在一起，用于时钟数据恢复电路的低等待时间和低锁定时间。

公开(公告)号：US20230170891A1

公开(公告)日：2023-06-01

申请号：US18051138

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonju LEE ,  Jiyoung KIM ,  Jaehyun PARK ,  Seuk SON ,  Sooeun LEE ,  Dongchul CHOI

IPC: H03K5/26 ,  H03K3/037

CPC classification number: H03K5/26 ,  H03K3/037 ,  H03K2005/00286

Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.