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公开(公告)号:US20240375227A1
公开(公告)日:2024-11-14
申请号:US18657146
申请日:2024-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: DONGHYUN KIM , JONGSEONG KO , DAEYONG KIM , JISU KIM , PYUNGKANG KIM , KIHONG PARK , JUNGJUN PARK , JUNGJOON PARK , JOOYOUNG PARK , JUNHYEOK PARK , HOSEOK SONG , CHIHO AHN , KONGWOO LEE , HYUNYOUNG LEE , CHUYOUNG CHOUNG , JEONGMIN HWANG
Abstract: A fastening device includes: a support portion including a first end portion, and a second end portion, and a central portion between the first and second end portions; a first pulley, a second pulley, and a third pulley rotatably disposed on the central portion, the first end portion, and the second end portion, respectively; a first connection portion and a second connection portion respectively rotatably disposed on the first and second end portions and respectively connected to the second and third pulleys; a first fastening tool and a second fastening tool respectively connected to the first and second connection portions; and a motor connected to the first pulley, wherein a force generated by the motor and provided to the first pulley is at least partially transmitted to the second and third pulleys to vary a distance between the first and second fastening tools.
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公开(公告)号:US20160043197A1
公开(公告)日:2016-02-11
申请号:US14820564
申请日:2015-08-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: CHEOL KIM , DONGHYUN KIM , MYEONGCHEOL KIM , DAEYONG KIM , CHULSUNG KIM
IPC: H01L29/66 , H01L21/02 , H01L21/768
CPC classification number: H01L29/6681 , H01L21/31116 , H01L21/76897 , H01L29/6656
Abstract: Provided are a semiconductor device and a fabrication method thereof. The semiconductor device may include a fin-shaped active pattern and a gate electrode provided on a substrate, first and second spacers provided on a sidewall of the gate electrode, impurity regions provided at both sides of the gate electrode, a contact plug electrically connected to one of the impurity regions, and a third spacer enclosing the contact plug and having a top surface positioned at substantially the same level as a top surface of the contact plug.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括鳍形有源图案和设置在基板上的栅电极,设置在栅电极的侧壁上的第一和第二间隔物,设置在栅电极两侧的杂质区,电连接到 一个杂质区,以及包围该接触插塞的第三间隔件,并且具有位于该接触插塞顶表面基本相同高度的顶表面。
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