公开(公告)号：US20250062252A1

公开(公告)日：2025-02-20

申请号：US18742833

申请日：2024-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeean Lee ,  Dongwon Kang ,  Changyeon Song ,  Sunguk Lee

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a redistribution insulation layer and a connection structure disposed on the redistribution insulation layer in a first direction and including a base layer, a metal pattern, and a cavity. A semiconductor chip is disposed on the redistribution insulation layer in the first direction. The semiconductor chip is spaced apart from the connection structure by a molding layer. The semiconductor chip and the molding layer are disposed in the cavity. The metal pattern is disposed on the redistribution insulation layer, at least partially between the base layer and the molding layer. The metal pattern includes a first metal pattern extending, in a second direction crossing the first direction, from an inner surface of the connection structure into the base layer and separating at least a portion of the base layer from at least a portion of the redistribution insulation layer.

公开(公告)号：US20250125247A1

公开(公告)日：2025-04-17

申请号：US18779913

申请日：2024-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeean Lee ,  Dongwon Kang ,  Jieun Park ,  Changyeon Song ,  Sunguk Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: An IC package includes a lower redistribution structure, a connection structure (with cavity) on the lower redistribution structure, a semiconductor chip in the cavity, a molding layer filling the cavity, covering the connection structure and the semiconductor chip, and having an upper through hole therein. An upper redistribution structure is provided that includes: an upper insulating layer on the molding layer, a first protrusion inside the upper through hole, and an upper redistribution pattern, which includes a first upper via pattern, inside the first protrusion. The upper through hole of the molding layer is located above the via structure of the connection structure, the first upper via pattern is electrically connected to the via structure of the connection structure, and a portion of the first upper line pattern of the upper redistribution structure is buried in the upper insulating layer.

公开(公告)号：US20250079382A1

公开(公告)日：2025-03-06

申请号：US18807488

申请日：2024-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeean Lee ,  Dongwon Kang ,  Dahee Kim ,  Changyeon Song ,  Sunguk Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: Provided is a semiconductor package including a lower package substrate including lower insulating layers, a first semiconductor device mounted on the lower package substrate, a core layer on the lower package substrate to be laterally spaced apart from the first semiconductor device, an encapsulation material surrounding the first semiconductor device and covering an upper portion of the core layer, an upper package substrate disposed on the encapsulation material, the upper package substrate including a first upper redistribution layer and a second upper redistribution layer; wherein a first line width and a first line spacing of a first fine pattern of the first upper redistribution pattern are greater than or equal to a corresponding second line width and a corresponding second line spacing of a second fine pattern of the second upper redistribution pattern, respectively.