公开(公告)号：US20230055450A1

公开(公告)日：2023-02-23

申请号：US17841858

申请日：2022-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Min CHOO ,  Hyuk Woo KWON ,  Dong Woo KIM ,  Byoung Deog CHOI

IPC: H01L27/108 ,  H01L49/02

Abstract: A semiconductor device including a first pad on a substrate extending in a first direction and a second direction, a lower electrode connected to and disposed on the first pad, first to third supporter layers disposed on a side wall of the lower electrode and sequentially spaced apart from each other in a third direction perpendicular to the first direction and the second direction, a dielectric film disposed on the lower electrode and the first to third supporter layers, and an upper electrode disposed on the dielectric film. At least one of a side wall of the lower electrode between the first supporter layer and the second supporter layer, and a side wall of the lower electrode between the second supporter layer and the third supporter layer includes a first portion including protrusions extending in the first direction and includes a second portion including no protrusions.

公开(公告)号：US20210320105A1

公开(公告)日：2021-10-14

申请号：US17355272

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Deog CHOI ,  Ji Woon IM

IPC: H01L27/108 ,  B82Y10/00 ,  H01L49/02

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering an upper part of the air spacer.

公开(公告)号：US20200381435A1

公开(公告)日：2020-12-03

申请号：US16682061

申请日：2019-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Deog CHOI ,  Ji Woon IM

IPC: H01L27/108 ,  H01L49/02 ,  B82Y10/00

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering an upper part of the air spacer.

公开(公告)号：US20220115442A1

公开(公告)日：2022-04-14

申请号：US17348912

申请日：2021-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeong Ju BAE ,  Seung-Heon LEE ,  Ik Soo KIM ,  Byoung Deog CHOI

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor memory device and associated methods, the device including first and second lower conductive lines extending in a first direction; a first middle conductive line on the first and second lower conductive lines and extending in a second direction; first and second memory cells between the first and second lower conductive lines and the first middle conductive line; an air gap support layer between the first and second memory cells; and a first air gap between the first and second memory cells and under the air gap support layer, wherein an upper surface of the air gap support layer lies in a same plane as the first and second memory cells, the first and second memory cells include first and second OTS layers and first and second phase-change layers, and the first air gap overlaps the first and second phase-change layers.