公开(公告)号：US20230363149A1

公开(公告)日：2023-11-09

申请号：US18077419

申请日：2022-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： So Hyeon Bae ,  Won Chul Lee ,  Byeong Jun Bae

IPC: H01L29/94

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10894

Abstract: A semiconductor memory device may include a substrate including a cell region and a peripheral region defined around the cell region, and a gate structure which may include sequentially stacked first, second, and third conductive layers including different materials, the first conductive layer including polysilicon. A capping layer may be on the third conductive layer, and a spacer may be on a sidewall of each of the first to third conductive layers and the capping layer. A first contact may extend through the capping layer and into the third conductive layer, with the first contact in contact with the second conductive layer, and separated from the first conductive layer. The first contact may include a first portion in the third conductive layer and a second portion in the capping layer. A width of the first portion may be greater than a width of the second portion in a horizontal direction.