公开(公告)号：US20170069828A1

公开(公告)日：2017-03-09

申请号：US15227953

申请日：2016-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baik-Woo LEE ,  Eun-Seok SONG ,  Young-Jae KIM ,  Jae-Gwon JANG

IPC: H01L43/02 ,  H01L43/08

CPC classification number: H01L23/552 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: In one embodiment, a semiconductor device comprising, a substrate comprising a wiring layer, a first conductive shielding layer disposed on the substrate and electrically isolated from the wiring layer, the first conductive shielding layer comprising a first bonding surface and a first end surface extending from the first bonding surface, a semiconductor chip disposed on the first conductive shielding layer, a molding member disposed over the first conductive shielding layer to cover the semiconductor chip, a second conductive shielding layer disposed over the first conductive shielding layer and the molding member, the second conductive shielding layer comprising a second bonding surface and a second end surface extending from the second bonding surface, and a bonding portion disposed between the first and second bonding surfaces, the bonding portion comprising a top surface and a bottom surface opposite to the top surface. The bottom surface of the bonding portion contacts the first bonding surface to form a first contact surface. The top surface of the bonding portion contacts the second bonding surface to form a second contact surface. An area of the second contact surface is larger than an area of the second end surface.

Abstract translation: 在一个实施例中，一种半导体器件，包括：衬底，其包括布线层，设置在衬底上并与布线层电隔离的第一导电屏蔽层，第一导电屏蔽层包括第一接合表面和第一端面， 所述第一接合表面，设置在所述第一导电屏蔽层上的半导体芯片，设置在所述第一导电屏蔽层上以覆盖所述半导体芯片的成型构件，设置在所述第一导电屏蔽层和所述模制构件上方的第二导电屏蔽层， 第二导电屏蔽层，包括从第二接合表面延伸的第二接合表面和第二端表面，以及设置在第一和第二接合表面之间的接合部分，接合部分包括顶表面和与顶表面相对的底表面 。 接合部分的底表面接触第一接合表面以形成第一接触表面。 接合部分的顶表面接触第二接合表面以形成第二接触表面。 第二接触面的面积大于第二端面的面积。