Abstract:
A display device includes sub-pixels. The first and third sub-pixels overlap in a first direction. The second sub-pixel is spaced from the first and third sub-pixels in a second direction. Each of the sub-pixels includes a pixel-circuit layer including a pixel circuit including first and second transistors, a data line, and a scan line, and a light-emitting-element layer on the pixel-circuit layer and including a light emitting element. The pixel circuit includes first to third pixel circuits in the first to third sub-pixels, respectively. The data line includes first to third data lines included in the first to third sub-pixels, respectively, and electrically connected to the first to third pixel circuits, respectively. The first to third data lines are adjacent. The second data line is not between the first and third data lines such that only one side of the second data line faces the first and third data lines.
Abstract:
A scan driver including a plurality of scan stages. A first scan stage among the plurality of scan stages includes first-to-sixth transistors and a first capacitor. The first transistor is connected to a first Q node, a first scan clock line, and a first scan line. A second transistor is connected to a first scan carry line and the first Q node. A third transistor is connected to a first sensing carry line and a second sensing carry line. A fourth transistor is connected to a first control line and the third transistor. A fifth transistor is connected to the fourth transistor, a second control line, and a first node. A first capacitor is connected to the fifth transistor. A sixth transistor is connected to a third control line, the first node, and the first Q node.
Abstract:
A scan driver for a display device includes a plurality of stages outputting scan signals. A first stage of the plurality of stages includes first to sixth transistors connected to a first carry clock line, a carry line, a previous carry line, and a second carry clock line. In a first frame period, the second carry clock line is configured to receive a second carry clock signal having at least one pulse with substantially the same phase as at least one of first pulses of a first carry clock signal to be applied to the first carry clock line.
Abstract:
A stage and a scan driver having the same. The stage outputs a scan signal and a sensing signal to a scan line and a sensing line, respectively. The stage includes a first controller configured to control a voltage of a sensing node and a driving node based on first to third control signals and a carry signal of the stage and another stage connected to the stage, a second controller configured to control a voltage of an inversion driving node based on a first carry clock signal, the voltage of the driving node, and the third control signal, and a first output buffer configured to output a second carry clock signal or a second low potential power as the carry signal in correspondence with the voltage of the driving node and the inversion driving node.
Abstract:
A scan driver including a plurality of scan stages. A first scan stage among the plurality of scan stages includes first-to-sixth transistors and a first capacitor. The first transistor is connected to a first Q node, a first scan clock line, and a first scan line. A second transistor is connected to a first scan carry line and the first Q node. A third transistor is connected to a first sensing carry line and a second sensing carry line. A fourth transistor is connected to a first control line and the third transistor. A fifth transistor is connected to the fourth transistor, a second control line, and a first node. A first capacitor is connected to the fifth transistor. A sixth transistor is connected to a third control line, the first node, and the first Q node.
Abstract:
An organic light-emitting display including a data driver connected to a plurality of data lines disposed in a first direction, a scan driver connected to a plurality of scan lines disposed in a second direction intersecting the first direction, and a display panel including a pixel group which includes first through fourth pixel units respectively connected to j-th through (j+3)-th data lines among the data lines. The first through fourth pixel units are connected to an i-th scan line among the scan lines and disposed in the first direction, where i and j are natural numbers equal to or greater than one.