公开(公告)号：US20160320674A1

公开(公告)日：2016-11-03

申请号：US15011795

申请日：2016-02-01

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Miseon SEO ,  Keumdong JUNG ,  Kihwan KIM ,  Jooyeon LEE ,  Munsoo PARK

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/134309 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345

Abstract: A liquid crystal display (“LCD”) device capable of easily setting up an accurate resistance ratio between thin film transistors, the LCD device includes a first substrate including a gate line and a data line, a second substrate opposing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first sub-pixel electrode in a first sub-pixel region of the first substrate, a second sub-pixel electrode in a second sub-pixel region of the first substrate, a first transistor connected to the gate line, the data line, and the first sub-pixel electrode, a second transistor connected to the gate line, the first transistor, and the second sub-pixel electrode, and a third transistor connected to the gate line, the second sub-pixel electrode, and a storage line, wherein one of the first, second, and third transistors includes a plurality of divided channel regions.

Abstract translation: 一种液晶显示器（“LCD”）器件，其能够容易地在薄膜晶体管之间建立精确的电阻比，所述LCD器件包括包括栅极线和数据线的第一衬底，与第一衬底相对的第二衬底，液体 第一基板和第二基板之间的第一子像素电极，第一基板的第一子像素区域中的第一子像素电极，第一基板的第二子像素区域中的第二子像素电极，第一晶体管 连接到栅极线，数据线和第一子像素电极，连接到栅极线的第二晶体管，第一晶体管和第二子像素电极，以及连接到栅极线的第三晶体管， 第二子像素电极和存储线，其中所述第一，第二和第三晶体管中的一个包括多个分割的沟道区。

公开(公告)号：US20210202759A1

公开(公告)日：2021-07-01

申请号：US16984789

申请日：2020-08-04

Applicant: Samsung Display Co., Ltd.

Inventor： Hyunjung LEE ,  Youngkuk KIM ,  Miseon SEO

IPC: H01L29/786 ,  H01L27/32

Abstract: A thin-film transistor substrate and a display apparatus including the same includes a first thin-film transistor on a substrate. The first thin-film transistor includes a first semiconductor layer having a first channel area, a first source area, and a first drain area; a first lower gate electrode between the substrate and the first semiconductor layer; a first upper gate electrode on the first semiconductor layer and overlapping the first channel area; and a first electrode layer on the first upper gate electrode and electrically connected to at least one of the first source area and the first drain area. The first lower gate electrode overlaps the first channel area and the first drain area.