公开(公告)号：US12052888B2

公开(公告)日：2024-07-30

申请号：US17141001

申请日：2021-01-04

Applicant: Samsung Display Co., Ltd.

Inventor： Youngjin Cho ,  Hyunwoong Kim ,  Joong-soo Moon ,  Seung-kyu Lee ,  Yangwan Kim

IPC: H10K59/126 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3275 ,  H10K59/121 ,  H10K59/131

CPC classification number: H10K59/1213 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3275 ,  H10K59/126 ,  H10K59/131

Abstract: Provided is pixel including a first transistor including a first drain region electrically connected to a light emitting diode, a first gate electrode, a first channel region overlapping the first gate electrode, and a first source region, a first sub-transistor including a first sub-gate electrode, a first sub-channel region overlapping the first sub-gate electrode, a first sub-drain region connected to the first gate electrode, and a first sub-source region, a second sub-transistor including a second sub-gate electrode, a second sub-channel region overlapping the second sub-gate electrode, a second sub-drain region connected to the first sub-source region, and a second sub-source region, and a shielding pattern overlapping the first sub-source region and the second sub-drain region and not overlapping the first sub-channel region, wherein a width of the first sub-channel region is greater than a width of the second sub-channel region.

公开(公告)号：US10943965B2

公开(公告)日：2021-03-09

申请号：US16406825

申请日：2019-05-08

Applicant: Samsung Display Co., Ltd.

Inventor： Youngjin Cho ,  Hyunwoong Kim ,  Joong-soo Moon ,  Seung-kyu Lee ,  Yangwan Kim

IPC: H01L27/32 ,  G09G3/3275 ,  G09G3/3225 ,  G09G3/3266

Abstract: Provided is pixel including a first transistor including a first drain region electrically connected to a light emitting diode, a first gate electrode, a first channel region overlapping the first gate electrode, and a first source region, a first sub-transistor including a first sub-gate electrode, a first sub-channel region overlapping the first sub-gate electrode, a first sub-drain region connected to the first gate electrode, and a first sub-source region, a second sub-transistor including a second sub-gate electrode, a second sub-channel region overlapping the second sub-gate electrode, a second sub-drain region connected to the first sub-source region, and a second sub-source region, and a shielding pattern overlapping the first sub-source region and the second sub-drain region and not overlapping the first sub-channel region, wherein a width of the first sub-channel region is greater than a width of the second sub-channel region.