公开(公告)号：US11937476B2

公开(公告)日：2024-03-19

申请号：US18143402

申请日：2023-05-04

Applicant: Samsung Display Co., Ltd.

Inventor： Jin Sung An ,  Sung Ho Kim ,  Yong Jae Kim ,  Yun Hwan Park ,  Yoon Jee Shin ,  Sug Woo Jung ,  Hyun Wook Choi

IPC: H10K59/131 ,  G09G3/3233 ,  H10K59/88

CPC classification number: H10K59/131 ,  G09G3/3233 ,  H10K59/88 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0861 ,  G09G2310/02

Abstract: A display device comprises a substrate; a circuit array layer comprising pixel drivers, data lines, first dummy lines, and second dummy lines; and a light emitting array layer. The display area comprises middle, first side, and second side regions. The data lines comprise first, second, and third data lines disposed in the middle, first side, and second side regions, respectively. The first dummy lines comprise a first data detour line disposed in the first side region and adjacent to a part of the second data line, and auxiliary lines. The second dummy lines comprise a second data detour line configured to connect the first data detour line to the third data line, and additional lines. The auxiliary lines comprise a bias auxiliary line to which a bias power is applied; and a second power auxiliary line to which a second power is applied.

公开(公告)号：US12185602B2

公开(公告)日：2024-12-31

申请号：US18437088

申请日：2024-02-08

Applicant: Samsung Display Co., Ltd.

Inventor： Jin Sung An ,  Sung Ho Kim ,  Yong Jae Kim ,  Yun Hwan Park ,  Yoon Jee Shin ,  Sug Woo Jung ,  Hyun Wook Choi

IPC: H10K59/131 ,  G09G3/3233 ,  H10K59/88

Abstract: A display device comprises a substrate; a circuit array layer comprising pixel drivers, data lines, first dummy lines, and second dummy lines; and a light emitting array layer. The display area comprises middle, first side, and second side regions. The data lines comprise first, second, and third data lines disposed in the middle, first side, and second side regions, respectively. The first dummy lines comprise a first data detour line disposed in the first side region and adjacent to a part of the second data line, and auxiliary lines. The second dummy lines comprise a second data detour line configured to connect the first data detour line to the third data line, and additional lines. The auxiliary lines comprise a bias auxiliary line to which a bias power is applied; and a second power auxiliary line to which a second power is applied.

公开(公告)号：US11842685B2

公开(公告)日：2023-12-12

申请号：US17813489

申请日：2022-07-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Jae Kim ,  In Jun Bae ,  Hyun Wook Choi

IPC: G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/08 ,  G09G2320/02 ,  G09G2320/0626 ,  G09G2330/021

Abstract: A pixel includes: a light emitting element; a first transistor generating a driving current flowing from a first power line to a second power line; a second transistor being turned on in response to a fourth scan signal; a third transistor being turned on in response to a second scan signal; a fourth transistor being turned on in response to a first scan signal; a fifth transistor being turned on in response to a third scan signal; a sixth transistor being turned off in response to a first emission control signal; a first capacitor; and a second capacitor. A period in which the second transistor is turned on and a period in which the third transistor is turned on do not overlap with each other.

公开(公告)号：US11557254B2

公开(公告)日：2023-01-17

申请号：US16984010

申请日：2020-08-03

Applicant: Samsung Display Co., Ltd.

Inventor： Na-Young Kim ,  Dong-Hwi Kim ,  Chul Ho Kim ,  Yun Hwan Park ,  Jin Jeon ,  Hyun Wook Choi

IPC: G09G3/3208 ,  G09G3/3266

Abstract: A pixel of an OLED display device includes a capacitor coupled between first and second nodes, first and second transistors, each including a gate receiving a respective initialization signal, a first terminal receiving a first power supply voltage, and a second terminal coupled to the capacitor, a third transistor including a first terminal coupled to a data line and a second terminal coupled to the first node, a fourth transistor including a gate coupled to the second node, a first terminal receiving the first power supply voltage, and a second terminal coupled to a third node, a fifth transistor including a first terminal coupled to the third node and a second terminal coupled to the second node, sixth and seventh transistors receiving a scan signal, eighth and ninth transistors receiving an emission signal, and an OLED.