公开(公告)号：US20210359688A1

公开(公告)日：2021-11-18

申请号：US17185813

申请日：2021-02-25

Applicant: Samsung Display Co., Ltd.

Inventor： Ki Hyun PYUN ,  Hee SooK PARK

IPC: H03L7/08 ,  G09G5/00

Abstract: A clock data recovery circuit includes a phase-locked loop circuit generating a multi-phase clock signal based on input data, the phase-locked loop circuit including a multi-rate phase detector being operable at an initial rate among a plurality of rates in an initial period; a lock detector generating a lock-enable signal by detecting a lock state of the phase-locked loop circuit; a dead zone calibration circuit determining an operational rate corresponding to a data rate of the input data among the plurality of rates in response to the lock-enable signal; and a digital block controlling the multi-rate phase detector to operate at the operational rate, and generating a calibration-enable signal. The dead zone calibration circuit determines whether the multi-phase clock signal is locked within a dead zone in response to the calibration-enable signal, and changes a phase of the multi-phase clock signal based on the multi-phase clock signal.