公开(公告)号：US20190333448A1

公开(公告)日：2019-10-31

申请号：US16503710

申请日：2019-07-05

Applicant: Samsung Display Co., Ltd.

Inventor： Chang Yeop KIM ,  Jin JEON

IPC: G09G3/3233 ,  G09G3/3225 ,  H01L27/32 ,  G09G3/3266 ,  G09G3/3275

Abstract: The present disclosure relates to a display device whose image quality is improved. A display device according to an embodiment of the present disclosure includes a first display area configured to include a plurality of first pixels which are disposed at least one horizontal line; a second display area configured to include a plurality of second pixels which are disposed in a plurality of horizontal lines; and an infrared (IR) light source configured to overlap the first display area in a plan view. The plurality of first pixels are set to be in a non-emission state during a period when the IR light source is driven.

公开(公告)号：US20180061315A1

公开(公告)日：2018-03-01

申请号：US15586402

申请日：2017-05-04

Applicant: Samsung Display Co., Ltd.

Inventor： Chang Yeop KIM ,  Jin JEON

IPC: G09G3/3233 ,  G09G3/3275 ,  G09G3/3266 ,  H01L27/32

CPC classification number: G09G3/3233 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3275 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0261 ,  G09G2320/0646 ,  G09G2330/021 ,  G09G2360/145 ,  H01L27/3248

Abstract: The present disclosure relates to a display device whose image quality is improved.A display device according to an embodiment of the present disclosure includes a first display area configured to include a plurality of first pixels which are disposed at least one horizontal line; a second display area configured to include a plurality of second pixels which are disposed in a plurality of horizontal lines; and an infrared (IR) light source configured to overlap the first display area in a plan view. The plurality of first pixels are set to be in a non-emission state during a period when the IR light source is driven.

公开(公告)号：US20180240382A1

公开(公告)日：2018-08-23

申请号：US15692609

申请日：2017-08-31

Applicant: Samsung Display Co., Ltd.

Inventor： Deok Young CHOI ,  Yong Jae KIM ,  Chang Yeop KIM ,  Jin JEON

IPC: G09G3/00 ,  G09G3/3266 ,  G09G3/3208 ,  G09G3/36 ,  H03F3/30 ,  H03F3/21

CPC classification number: G09G3/003 ,  G09G3/3208 ,  G09G3/3266 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2310/0224 ,  G09G2310/0286 ,  H03F3/211 ,  H03F3/3022

Abstract: A stage circuit including an input unit controlling voltages of a first node and a second node by using a shift pulse or a gate start pulse input to a first input terminal, a first clock signal input to a second input terminal, a second clock signal input to a third input terminal, a first power supply input to a first power supply input terminal and a second power supply input to a second power supply input terminal, and a first output unit receiving a third clock signal from a fourth input terminal and the second power supply from the second power supply input terminal and outputting a high-level scan signal to a first output terminal corresponding to the voltages of the first node and the second node.