公开(公告)号：US20180166521A1

公开(公告)日：2018-06-14

申请号：US15728755

申请日：2017-10-10

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Subin BAE ,  Shinil CHOI ,  Changok KIM ,  Chulmin BAE ,  Sanggab KIM ,  Sunghoon YANG ,  Yeoungkeol WOO ,  Yugwang JEONG

IPC: H01L27/32

CPC classification number: H01L27/3248 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3258 ,  H01L27/3276 ,  H01L29/78618 ,  H01L2227/323

Abstract: A display device includes a thin film transistor, a gate insulting layer, an interlayer insulating layer, a data line, a spacer, and a pixel. The thin film transistor includes a semiconductor layer and a gate electrode. The semiconductor layer includes a source region and a drain region on respective sides of the channel region. The gate insulating layer is between the semiconductor layer and the gate electrode. The interlayer insulating layer covers the thin film transistor. The data line contacts the semiconductor layer via a hole passing through the gate insulating layer and the interlayer insulating layer. The spacer is on an inner wall of the hole and contacting the data line. The pixel electrode is electrically connected to the thin film transistor.

公开(公告)号：US20230309343A1

公开(公告)日：2023-09-28

申请号：US18089457

申请日：2022-12-27

Applicant: Samsung Display Co., LTD.

Inventor： Keunwoo KIM ,  Taewook KANG ,  Yeoungkeol WOO ,  Woo-Seok JEON

IPC: H10K59/121

CPC classification number: H10K59/1213 ,  H10K59/1216

Abstract: A display device includes a substrate, an active pattern disposed on the substrate, and including a first area, a second area, a (1-1)th channel area, a (1-2)th channel area, and a third area disposed between the (1-1)th channel area and the (1-2)th channel area, a first insulating layer disposed on the substrate and covering the active pattern, a second insulating layer which is disposed on the first insulating layer and in which an opening overlapping the (1-2)th channel area, the second area, and the third area is defined, a first gate electrode disposed on the first insulating layer and overlapping the (1-1)th channel area the (1-2)th channel area, respectively, and a high dielectric layer disposed on the first insulating layer and the second insulating layer, covering the first gate electrode, and filling the opening.