公开(公告)号：US20250140141A1

公开(公告)日：2025-05-01

申请号：US18926720

申请日：2024-10-25

Applicant: Samsung Display Co., LTD.

Inventor： EOK SU KIM ,  SOYOUNG KOO ,  JONGDO KEUM ,  HYUNGJUN KIM ,  GEUNCHUL PARK

IPC: G09G3/00 ,  G09G3/3266 ,  H10K59/131

Abstract: A test circuit includes: a metal pattern disposed in a first area; a test gate driver disposed in a second area adjacent to the first area and including a plurality of test stages, each of which outputs a test gate signal; and a plurality of test gate lines overlapping the metal pattern in a plan view, connected to the plurality of test stages, respectively, each including a first metal line and a second metal line connected in series with the first metal line, and which receives the test gate signal.