公开(公告)号：US20190012143A1

公开(公告)日：2019-01-10

申请号：US16114958

申请日：2018-08-28

Applicant: STMicroelectronics S.r.l.

Inventor： David Vincenzoni ,  Samuele Raffaelli

IPC: G06F7/544

CPC classification number: G06F7/5443

Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.

公开(公告)号：US10089078B2

公开(公告)日：2018-10-02

申请号：US15275037

申请日：2016-09-23

Applicant: STMicroelectronics S.r.l.

Inventor： David Vincenzoni ,  Samuele Raffaelli

IPC: G06F7/48 ,  G06F7/544

Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.

公开(公告)号：US10437558B2

公开(公告)日：2019-10-08

申请号：US16114958

申请日：2018-08-28

Applicant: STMicroelectronics S.r.l.

Inventor： David Vincenzoni ,  Samuele Raffaelli

IPC: G06F7/48 ,  G06F7/544

Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.