CENTRALIZED DIGITAL MUTE AND VOLUME CONTROL
    1.
    发明公开

    公开(公告)号:US20230418548A1

    公开(公告)日:2023-12-28

    申请号:US17846586

    申请日:2022-06-22

    CPC classification number: G06F3/165

    Abstract: An audio device includes a gain step selection circuit that receives a different requested gain value and an associated requested step size from each of a plurality of sources, compares each requested gain value to a same feedback gain value and generates a polarity based thereupon, performs step polarization on each requested step size as a function of the generated polarity therefor to thereby generate a plurality of step values, and outputs a least of the plurality of step values as an output step value. An accumulator circuit generates a current input gain value based upon the output step value and the feedback gain value, and then updates the feedback gain value to be equal to the current input gain value. A normalizing circuit multiplies an input data value by the current input gain value and applies a truncation function to a result thereof to produce an output data value.

    NOISE SHAPER FADER
    3.
    发明公开
    NOISE SHAPER FADER 审中-公开

    公开(公告)号:US20230336136A1

    公开(公告)日:2023-10-19

    申请号:US17719613

    申请日:2022-04-13

    CPC classification number: H03G3/344 H04R3/00 H04R2430/01 H03G2201/103

    Abstract: A digital audio playback circuit includes a noise shaping circuit configured to receive an input digital audio signal, and a digital to analog converter (DAC) configured to convert the input digital audio signal to a pre-amplified output analog audio signal according to a gain ramp defined by a gain control signal. A muting circuit is configured to compare input digital audio signal to a threshold and assert a mute control signal when the input digital audio signal is below the threshold. An analog gain control ramp circuit is configured to generate the gain control signal in response to the mute control signal to cause the gain ramp to ramp down. An amplifier is configured to amplify the pre-amplified output analog audio signal for playback by an audio playback device.

    NOISE SHAPER VARIABLE QUANTIZER
    4.
    发明公开

    公开(公告)号:US20230421167A1

    公开(公告)日:2023-12-28

    申请号:US17846520

    申请日:2022-06-22

    CPC classification number: H03M1/0668 H03M1/0648 H03M1/0626

    Abstract: A signal processing circuit includes a filter generating a quantizer input signal from a noise shaping input signal and a quantizer output signal. A quantizer divides the quantizer input signal by a scaling factor to produce a noise shaping output signal and multiplies the noise shaping output signal by the scaling factor to produce the quantizer output signal. Receiver circuitry scales the quantizer output signal by a second scaling factor. A dynamic range optimization circuit compares a current value of the noise shaping input signal to a threshold value, lowers or raises the scaling factor in response to the comparison, and proportionally lowers or raises the scaling factor such that a ratio between the scaling factor and second scaling factor remains substantially constant.

    SWITCHING CIRCUIT, CORRESPONDING DEVICE AND METHOD

    公开(公告)号:US20230412129A1

    公开(公告)日:2023-12-21

    申请号:US18206331

    申请日:2023-06-06

    CPC classification number: H03F3/2173 H03F2200/03 H03F2200/171 H03F2200/351

    Abstract: A switching circuit includes first and second half bridges supplying an electrical load via filter networks. During alternate switching sequences a first transistor pair (high-side in one half bridge and low-side in the other half bridge) is switched to a non-conductive state, and a second transistor pair (high-side in the other half bridge and low-side in the one half bridge) is switched to a conductive state. A current flow line is provided by an inductance, a first switch and a second switch between outputs of the half bridges. In a medium-high power mode, the first and second switches are in the conductive state between switching the first pair of transistors to the non-conductive state and the second pair of transistors to the conductive state. In a low or quiescent power mode, switching the first and second switches to the conductive state is refrained due to application of a longer delay.

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