公开(公告)号：US20030149831A1

公开(公告)日：2003-08-07

申请号：US10331177

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F012/00

CPC classification number: G06F11/1072

Abstract: A decoding structure for a memory device with a control code is used in a memory including a matrix of memory cells grouped into pages to each of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel. The decoding structure selectively connects each reading element to a plurality of memory cells, and selectively connects each memory cell to a plurality of reading elements.

Abstract translation: 具有控制码的存储器件的解码结构被用于存储器中的存储器，该存储器包括被分组成一页的存储器单元矩阵，每个存储器单元的一个控制信息块相关联，以及多个用于读取多个页面的读取元件 平行。 解码结构将每个读取元件选择性地连接到多个存储单元，并且将每个存储单元选择性地连接到多个读取元件。