公开(公告)号：US20030231538A1

公开(公告)日：2003-12-18

申请号：US10331135

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Danilo Rimondi ,  Cosimo Torelli

IPC: G11C007/00

CPC classification number: G11C7/20 ,  G11C11/419

Abstract: A memory cell comprises a first and a second inverters connected in a latch configuration. The inverters have respective first and second means for receiving a first and a second voltage supplies, respectively. The cell also comprises means, responsive to a memory cell selection signal, for selectively connecting an input of at least one of the first and second inverter to at least one respective input/output data line, carrying an input datum to be written in the memory cell in a memory cell write operation and an output datum read from the memory cell in a memory cell read operation. For-flash-clearing the memory cell, means are provided for switching at least one of the first and second voltage supply receiving means of at least one of the first and second inverters between the first voltage supply and the second voltage supply. The memory cell is particularly adapted to implement a flash-clear function in a memory device.

Abstract translation: 存储单元包括以锁存配置连接的第一和第二反相器。 逆变器具有分别用于接收第一和第二电压源的相应的第一和第二装置。 单元还包括响应于存储器单元选择信号的装置，用于将第一和第二反相器中的至少一个的输入选择性地连接到至少一个相应的输入/输出数据线，承载要写入存储器的输入数据 在存储单元读取操作中存储单元写入操作和从存储器单元读取的输出数据。 为了闪存清除存储单元，提供了用于在第一电压源和第二电压源之间切换第一和第二逆变器中的至少一个的第一和第二电压供应接收装置中的至少一个的装置。 存储器单元特别适于在存储器件中实现闪光功能。

公开(公告)号：US20030026150A1

公开(公告)日：2003-02-06

申请号：US10253217

申请日：2002-09-24

Applicant: STMicroelectronics S.r.I.

Inventor： Danilo Rimondi

IPC: G11C011/00 ,  G11C007/00

CPC classification number: G11C11/412

Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided. According to the method, the level of the bit line is set in accordance with data to be written, the memory cell is precharged so as to force the output of one of the inverters of the memory cell to a predetermined logic level, and the word line is activated to couple the bit line to the memory cell.