公开(公告)号：US20030218480A1

公开(公告)日：2003-11-27

申请号：US10407801

申请日：2003-04-04

Applicant: Indian ST (STMicroelectronics Pvt. Ltd.)

Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

IPC: H03K019/173

CPC classification number: H03K19/1774 ,  H03K19/17784

Abstract: An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

Abstract translation: 一种包含一个或多个数字同步顺序逻辑块的电子电路，其中至少一个在操作期间被选择或取消选择。 电子电路包括一种降低功耗的改进的时钟分配方案，包括识别装置，用于确定每个所述可取消同步顺序逻辑块的选择/取消选择状态，耦合到禁用装置，用于禁止每个取消选择的同步顺序逻辑块的时钟输入。

公开(公告)号：US20040008055A1

公开(公告)日：2004-01-15

申请号：US10449750

申请日：2003-05-29

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Namerita Khanna ,  Parvesh Swami ,  Deepak Agarwal

IPC: H03K019/177

CPC classification number: H03K19/1776 ,  H03K3/012 ,  H03K3/037 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17784

Abstract: A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Abstract translation: 一种可编程逻辑器件，用于为顺序逻辑和数据存储功能提供功率消耗降低，包括至少一个电路装置，其可配置为在电路时钟选定的一个或两个边缘上工作的双边沿触发触发器。

公开(公告)号：US20030214321A1

公开(公告)日：2003-11-20

申请号：US10407802

申请日：2003-04-04

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

IPC: H03K019/173

CPC classification number: H03K19/17736

Abstract: An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

Abstract translation: 一种改进的可编程逻辑设备架构，其通过在设备中的任何其他PLB上访问任何可编程逻辑块（PLB）的域中的定义的电路元件来提供资源的更有效的利用，通过在路由结构中并入选择性地连接 将PLB域中的电路元件的输入或输出连接到将所有PLB连接在一起的公共互连矩阵。