公开(公告)号：US09473135B2

公开(公告)日：2016-10-18

申请号：US14500076

申请日：2014-09-29

Applicant: STMicroelectronics International N.V.

Inventor： Paras Garg ,  Rajesh Yadav ,  Saiyid Mohammad Irshad Rizvi ,  Ravinder Kumar

IPC: H03K3/00 ,  H03K17/687 ,  H03K19/0185

CPC classification number: H03K17/687 ,  H03K19/0185 ,  H03K2217/0018

Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

Abstract translation: 驱动电路包括耦合在集成电路的第一电源节点和输出焊盘之间的第一驱动晶体管，以及耦合在第二电源节点和输出焊盘之间的第二驱动晶体管。 第一驱动晶体管和第二驱动晶体管由控制信号控制。 体偏置发生器电路被配置为将可变第一体偏置施加到第一晶体管，并将可变第二体偏置施加到第二晶体管。 可变的第一和第二体偏置作为控制信号和输出焊盘处的电压的函数产生。

公开(公告)号：US20150200632A1

公开(公告)日：2015-07-16

申请号：US14153119

申请日：2014-01-13

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Rajesh Yadav

IPC: H03F1/30 ,  H03F3/45 ,  H03K17/687

CPC classification number: H03K17/687 ,  H03F3/45183 ,  H03F3/45753 ,  H03F2200/447 ,  H03F2203/45341 ,  H03K3/3565 ,  H03K5/2481

Abstract: A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages.

Abstract translation: 将在第一晶体管处接收的第一信号与在第二晶体管处接收的第二信号进行比较，考虑滞后值以产生比较输出。 第一和第二晶体管中的至少一个具有浮动体积。 开关电路根据比较输出选择性地将第一和第二体偏置电压施加到第一或第二晶体管的浮动体。 设置滞后值的第三和第四输入信号在第三和第四晶体管处被接收，并被比较以产生差分输出。 第三和第四晶体管中的至少一个具有浮动体积。 差分放大器确定用于施加到第三和第四晶体管中的至少一个的浮动体的差分输出之间的差异，并进一步用作第一和第二体偏置电压之一。

公开(公告)号：US09432015B2

公开(公告)日：2016-08-30

申请号：US14153119

申请日：2014-01-13

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Rajesh Yadav

IPC: H03K5/22 ,  H03K17/687 ,  H03F3/45 ,  H03K5/24 ,  H03K3/3565

CPC classification number: H03K17/687 ,  H03F3/45183 ,  H03F3/45753 ,  H03F2200/447 ,  H03F2203/45341 ,  H03K3/3565 ,  H03K5/2481

Abstract: A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages.

Abstract translation: 将在第一晶体管处接收的第一信号与在第二晶体管处接收的第二信号进行比较，考虑滞后值以产生比较输出。 第一和第二晶体管中的至少一个具有浮动体积。 开关电路根据比较输出选择性地将第一和第二体偏置电压施加到第一或第二晶体管的浮动体。 设置滞后值的第三和第四输入信号在第三和第四晶体管处被接收，并被比较以产生差分输出。 第三和第四晶体管中的至少一个具有浮动体积。 差分放大器确定用于施加到第三和第四晶体管中的至少一个的浮动体的差分输出之间的差异，并进一步用作第一和第二体偏置电压之一。

公开(公告)号：US20160094217A1

公开(公告)日：2016-03-31

申请号：US14500076

申请日：2014-09-29

Applicant: STMicroelectronics International N.V.

Inventor： Paras Garg ,  Rajesh Yadav ,  Saiyid Mohammad Irshad Rizvi ,  Ravinder Kumar

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H03K19/0185 ,  H03K2217/0018

Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

Abstract translation: 驱动电路包括耦合在集成电路的第一电源节点和输出焊盘之间的第一驱动晶体管，以及耦合在第二电源节点和输出焊盘之间的第二驱动晶体管。 第一驱动晶体管和第二驱动晶体管由控制信号控制。 体偏置发生器电路被配置为将可变第一体偏置施加到第一晶体管，并将可变第二体偏置施加到第二晶体管。 可变的第一和第二体偏置作为控制信号和输出焊盘处的电压的函数产生。