公开(公告)号：US20250141653A1

公开(公告)日：2025-05-01

申请号：US18920028

申请日：2024-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Matteo COLOMBO ,  Augusto Andrea ROSSI ,  Jerome DEROO

IPC: H04L7/00 ,  H03L7/085 ,  H04L7/033 ,  H04L7/04

Abstract: An electronic digital system includes a digital core and a Serializer Deserializer module. A FIFO device of the core reads and writes on a set of buses coupled to said Serializer Deserializer module. The Serializer Deserializer module transmits data read from the FIFO architecture device on a set of buses as a corresponding serial signals transmitted by transmitters. The serial signals and corresponding transmitters are logically grouped. The transmitters include PLL circuits generating PLL clocks, using as reference a cluster transmitter reference clock common, to a respective cluster of transmitters controlling a frequency of serialization operation and low frequency clocks obtained by the PLL clocks according to one or more groups corresponding to group of buses.