公开(公告)号：US20230088967A1

公开(公告)日：2023-03-23

申请号：US17944793

申请日：2022-09-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Jean-Marc VOISIN

IPC: H01L27/02 ,  H01L23/64 ,  H01L21/768

Abstract: The integrated circuit includes a logic part including standard cells arranged in parallel rows along a first direction and in an alternation of complementary semiconductor wells. Among the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted over the length of the capacitive filling structure so that the first well occupies in the second direction the width of the two adjacent rows of the capacitive filling structure. A conductive structure electrically connects the second well on either side of the capacitive filling structure.