公开(公告)号：US11171034B2

公开(公告)日：2021-11-09

申请号：US16707614

申请日：2019-12-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Gouraud ,  Delia Ristoiu

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06

Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

公开(公告)号：US11901216B2

公开(公告)日：2024-02-13

申请号：US17496411

申请日：2021-10-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Gouraud ,  Delia Ristoiu

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/7621 ,  H01L29/0649

Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.