公开(公告)号：US20170179932A1

公开(公告)日：2017-06-22

申请号：US14973473

申请日：2015-12-17

申请人： SILICON LABORATORIES INC.

发明人： CARL H. ALELYUNAS ,  David Anderton ,  Nicholas R. Berkner ,  Yue Zhao ,  Thomas G. Ragan

IPC分类号： H03H21/00

CPC分类号： H03H17/0294 ,  H03H17/04 ,  H03H17/0461

摘要： An apparatus includes a plurality of delay elements, a plurality of multipliers and an accumulator to form a biquad stage; and a precision logic circuit. The biquad stage includes feedback paths; at least one feedback path has an adjustable bit precision; and the precision logic is adapted to regulate the bit precision of the feedback path(s) based at least in part on at least one parameter that is associated with the biquad stage.

公开(公告)号：US09954515B2

公开(公告)日：2018-04-24

申请号：US14973473

申请日：2015-12-17

申请人： SILICON LABORATORIES INC.

发明人： Carl H. Alelyunas ,  David Anderton ,  Nicholas R. Berkner ,  Yue Zhao ,  Thomas G. Ragan

IPC分类号： G06F7/48 ,  H03H21/00

CPC分类号： H03H17/0294 ,  H03H17/04 ,  H03H17/0461

摘要： An apparatus includes a plurality of delay elements, a plurality of multipliers and an accumulator to form a biquad stage; and a precision logic circuit. The biquad stage includes feedback paths; at least one feedback path has an adjustable bit precision; and the precision logic is adapted to regulate the bit precision of the feedback path(s) based at least in part on at least one parameter that is associated with the biquad stage.