公开(公告)号：US20150113236A1

公开(公告)日：2015-04-23

申请号：US14590106

申请日：2015-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWAN-HO KIM ,  Jong-In Kim ,  Young-wook Jang ,  Dae-woong Kim ,  Bong-chun Kang

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0679 ,  G06F13/4239

Abstract: A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.