Abstract:
A mobile system includes a SOC and PMIC. The SOC includes a first signal processing circuit and a second signal processing circuit, and generates a dynamic voltage scaling (DVS) control signal based on operating states of the first signal processing circuit and the second signal processing circuit. The PMIC generates a supply voltage whose magnitude is controlled in response to the DVS control signal, and provides the supply voltage to the first signal processing circuit and the second signal processing circuit through a single power rail.
Abstract:
In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.
Abstract:
A mobile system includes a SOC and PMIC. The SOC includes a first signal processing circuit and a second signal processing circuit, and generates a dynamic voltage scaling (DVS) control signal based on operating states of the first signal processing circuit and the second signal processing circuit. The PMIC generates a supply voltage whose magnitude is controlled in response to the DVS control signal, and provides the supply voltage to the first signal processing circuit and the second signal processing circuit through a single power rail.